Scholarlink

With shrinking feature sizes and increased chip sizes, the average delay of a logic gate is now dominated by the interconnection (metal wires) rather than by the transistor itself. Most of the potential electrical problems, such as cross talk, critical timing, substrate bounce, clock skew, etc., are related to the signal propagation and/or high (peak) currents through these metal wires.

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

Robustness of Nanometer CMOS Designs: Signal Integrity, Variability and Reliability

  • 章节

  • 发表日期：

    2025年

查看全文
  • Harry Veendrick

摘要

With shrinking feature sizes and increased chip sizes, the average delay of a logic gate is now dominated by the interconnection (metal wires) rather than by the transistor itself. Most of the potential electrical problems, such as cross talk, critical timing, substrate bounce, clock skew, etc., are related to the signal propagation and/or high (peak) currents through these metal wires.