Power Consumption Modelling for Symmetric Block Encryption Algorithms

The modeling of side channel leaks of power consumption during executing cryptographic algorithms is one of the perspective research areas in the field of security of cyber-physical systems. The use of algorithmically robustness ciphers may contain vulnerabilities based on the analysis of additional data sources (description of algorithm execution processes on real physical devices). Various side channels are distinguished, which are the source of such additional data, for example, the operation’s execution time, electromagnetic and acoustic emitting accompanying calculations, power consumption of devices and etc. The article presents the modeling of power consumption leaks performed in ELMO software for cryptographic algorithms: Advanced Encryption Standard (AES), PRESENT, Kalina (DSTU 7624:2014). Based on the performance of statistical tests, processor instructions containing leaks for each of the observed ciphers were identified. Assessment of instructions with leaks were made by comparison power consumption traces for fixed-input and power consumption traces for random-inputs (total quantity of traces is 104).