A 17ps Two Channel TDC System Based on XILINX ZYNQ 7000 SoC

In this work, a high-resolution two-channel time-to-digital converter (TDC) based on the Zynq 7000 SoC device is proposed and tested. TDC channels include a coarse counter, a fine counter, and a memory block. The Internal Tapped Delay line (TDL) method with a dedicated carry chain structure was used for fine time measurement. A 350 MHz system clock was used as a counter clock, and a timestamp was obtained by combining a 24-bit course counter with an 8-bit fine counter. A FPGA Block Random-access memory (RAM) was used to store 4096 32-bit timestamps, where Zynq ARM processor is using to read recorded data and print it over the UART port. Proposed TDC system, implemented in the PYNQ-Z2, which is a low-cost Zynq 7000 development board. The experiment result shows that the precision of TDC is 17.01.3 ps (RMS), which can be investigated in ToF measurement.