Compressors Using Modified Sorting and Parallel Counting

Multiplier is an utmost important and key element in the area of digital signal processing units, mobile computing, and embedded systems. To obtain the multiplication result quickly it is necessary to design an efficient process to add all the partial products in less time. Therefore, in this paper, we have designed and developed a modified compressor to add partial products of multiplier. In order to achieve this, we have designed a new sorting circuit for 3-bit, and 4-bit, to reduce the delay. The (7,3) compressor is constructed using 3-bit and 4-bit sorting circuits and found that the proposed design is 8.46%, 15.64%, 24.77%, 22.78% and 31.16% better than other designs in delay, area, power, area delay product and power delay product, respectively. Further, (15,4) compressor is constructed using the two (7,3) compressor and it performs 48.92%, 42.92%, 45.54%, and 39.15% better than other designs in area, power, area delay product and power delay product, respectively. Similarly, (31,5) compressor is constructed using the two (15,4) compressors and observed that our design is 8.07%, 52.83%, 39.45%, 53.33%, and 40.09% better than other designs in delay, area, power, area delay product and power delay product, respectively.