Quantum Computing Based Gate Level Optimizer for Digital Electronics

An indispensable procedure in the logical synthesis phase of the VLSI-IC design flow is the optimization of the digital circuit. Additionally, the electronic circuits are represented as Boolean expressions using the conventional logic gates as operators. Using unaltered Boolean expressions for IC design frequently results in unfavorable features in an IC, such as an increase in power, chip area, and cost, which lowers the efficiency. This research focuses on optimizing electronic circuit equations, by reducing the number of gates to achieve the same results as the original equations. In the case of traditional approaches, the complexity for an optimal solution increases considerably with an increase in operands and operator count. On the other hand, quantum computing, with the support of the quantum superposition principle, reduces the intricacy of finding effective answers efficiently. This methodology is not only effective in IC design but also beneficial in the execution of Boolean functions in circuits. Simulations are carried out on Vivado software using Verilog for observing IC performance parameters to establish a comparison between the original and optimized equations. The experimental results demonstrate an improvement in the speed of operations and a decrease in power consumption and resource usage. As a result of a drop in gate count, the space occupied by the IC and cost of production will reduce, benefitting the electronics industry. This paper contributes to the application of quantum computing in electronics manufacturing.