Dedicated FPGA Resources in Improving Power Efficiency of Implementations of BLAKE3 Hash Function

The BLAKE cryptographic hash functions can be efficiently coded in software but their hardware realizations are not as fast and power-effective as those of alternative algorithms. This paper evaluates possible reductions in power consumption of BLAKE3 FPGA implementations thanks to realization of the binary summations with dedicated DSP resources rather than with logic cells inside the programmable array. The analysis took into account different possible organizations of the method in hardware: starting from the typical iterative architecture (with one instance of the cipher round), derived high-throughput versions with 2, 4 and 6-stage pipelining were also analyzed. The results came from simulation of the designs fully implemented in a Spartan-7 device; they indicate that replacing the “in-the-array” adders with 7-series’s DSP48E1 elements can significantly reduce high dynamic power consumption which plagued the standard non-pipelined BLAKE3 architecture, but also reveal limitations of this approach in other cases. In addition to discussing one possible way of power reduction in this specific cipher, the paper can also be seen as another case study of an improvement in FPGA implementation made possible by taking advantage of (otherwise unused) specialized resources available beside the programmable array.