Styles for Describing Reliable Finite State Machines in Verilog HDL

Improving the reliability and designing of fault-tolerant finite state machines (FSMs) is an important task. There are many known methods for designing reliability FSMs. In these methods, a change of one or two bits in the FSM state register is most often considered as a fault. Structural models of robust Moore FSM have been presented in [9], which allow us to detect invalid input and output vectors both in each state and for the whole FSM, an invalid code of the present and next state, and invalid transitions between states. This paper discusses the Verilog HDL description styles of these structural models of robust FSMs, as well as the combined structural models. Experimental studies have shown that the considered structural models insignificantly increase the area of the original FSM, and for some structures the area even decreases. At the same time, the performance of the original FSM changes insignificantly, and for some structures it increases by 35–37%.