FPGA Implementation of a Decoder with Low-Density Parity Checks Based on the Minimum Sum Algorithm for 5G Networks

The scope of application of codes with low density parity checks and their role in the 5th generation mobile communication networks are considered. The mathematical apparatus of coding with low density parity checks is disclosed. A generalized and detailed decoder architecture optimized for solutions for 5G mobile networks is proposed. Fragments of source code in field-programmable gate array (FPGA) Verilog programming language are presented. In the Xilinx Vivado development environment, using developed test programs, modeling of both some individual project modules and the decoder macromodule was carried out. The results of compiling the decoder project with an analysis of the involved resources of the selected FPGA are presented.