Analysis of Placement in FPGA Using Genetic and Hybrid Genetic and Simulated Annealing Algorithms

This research study presents an analysis of Field Programmable Gate Array (FPGA) placement using Genetic Algorithm (GA) and Simulated Annealing (SA) algorithms. FPGA placement is a critical step in the design process, influencing factors such as wire length, circuit performance, and computational efficiency. In this study, we investigate the performance of GA and SA algorithms individually and in combination (hybrid GA-SA) across a range of circuit sizes, utilizing the MCNC benchmark suite. Our analysis includes metrics such as convergence rate, bounding box cost, wire length, and computational time. The results indicate that GA tends to converge faster than SA for placement tasks, regardless of circuit size. However, the hybrid GA-SA approach outperforms both GA and SA in terms of bounding box cost, leading to reduced wire length and improved circuit efficiency. Overall, this study provides valuable insights into the efficacy of GA, SA, and their combination for FPGA placement, offering guidance for optimizing placement strategies in FPGA design.