An Overview of Formal Verification of Network-on-Chip (NoC) Methods

Network-on-Chip (NoC) architectures are critical for the performance of manycore systems, but their growing complexity demands robust verification methods. This paper presents a comprehensive overview of most famous formal verification methods applied to NoC, emphasizing the importance of such practices in ensuring communication reliability. We examine into the challenges of NoC verification, such as ensuring deadlock and livelock freedom and protocol correctness. The paper evaluates model checking and theorem proving as pivotal tools for analyzing NoC properties, highlighting their impact on performance and scalability. Our findings demonstrate that rigorous formal verification is indispensable for the advancement of NoC designs. This work aims to guide future research by providing a synthesized compendium of the most prominent formal verification techniques, thus fostering enhanced reliability in NoC communications.