Fundamentals of Low-Power Neuromorphic Circuit Design with Spiking Neural Networks (SNNs)

Spiking neural networks (SNNs) have existed since the late twentieth century and continue to undergo development. Recent years have seen a remarkable interest in such biologically plausible networks in several real-life applications. SNNs closely emulate the behaviour of neurons in biological nervous systems, with synapses playing a crucial role in facilitating communication between different neurons. A synapse circuit based on an analogue CMOS suitable for VLSI implementation has been devised in this book chapter. This circuit features a time constant that can be easily and manually adjusted by the user. Leveraging the nonidealities of real transistors, which exhibit minimal leakage currents at the subthreshold level, enables the circuit to maintain very low power consumption. This is particularly advantageous considering that a network comprising multiple neurons and synapses would otherwise consume a significant amount of power. The circuit implements a simple first-order system utilizing a voltage signal with a very narrow pulse width as a spike input, mimicking the output of a presynaptic neuron. The design methodology is drawn, and the circuit’s performance is validated through successful simulations using LTspice. An enhanced circuit design has been proposed for readers to analyse and extend. The proposed design in this chapter introduces an easily adjustable time constant, with separate constants for the rise and fall of the synaptic potentials. This dual time constant approach offers greater biological plausibility, mirroring the distinct time constants observed in real biological synapses where the rising phase is considerably faster than the decaying phase. Additionally, the new design ensures that all transistors operate within the subthreshold region, in contrast to the circuit design, where certain transistors may occasionally operate in the triode region, leading to deviations from the intended first-order operation and introducing delays in the system. Both designs are compared through graphical representations of simulation outputs and circuit analyses. This chapter will help readers gain an in-depth understanding of SNNs and their prototyping at the circuit level.