Conclusion and Future Outlook

This book presents the PLL modulation architecture and circuit blocks for low-power and high-performance chirp synthesis and verified using two 28 nm prototype chips. The designs will further push the performance of the FMCW PLLs, by combining innovative mixed-signal processing and calibration techniques with Charge-Integrating Digital-to-Analog Converter (QDAC) as a key building block. Besides the exclusive LO generation, a PLL can also be used for radar signal demodulation. An outlook into the PLL architecture for LO generation, transmission and reception is provided in this chapter. Future researches can further explore these innovative architectures for use in FMCW radar systems.