A 16 GHz Duty-Cycled Charge Pump PLL-Based Chirp Synthesizer

In this chapter a duty cycling scheme is introduced to reduce the overall system power consumption. A CP-PLL architecture is adopted to enable a fast startup and robust fast relocking in a duty cycled environment. To enable background calibration in a CP-PLL, a time domain sign extraction mechanism with DC phase offset correction is proposed. Analog nonidealities, such as two-point gain imbalance and the DTC gain error are background calibrated, ensuring a robust operation with PVT. The design choices of each PLL building blocks are evaluated and key building blocks design are described. The 16 GHz chirp generator achieves a 29.3 MHz/ \(\upmu \) s chirp-slope with 41 kHz rms-frequency-error for 1.5 GHz chirp-bandwidth while consuming 16.5 mW power. The modulator can be used in a heavily duty-cycled regime, thanks to its robust below 1  \(\upmu \) s PLL phase/frequency lock time.