A 10 GHz Sub-Sampling PLL Chirp Synthesizer Using a Charge-Integrating DAC

This chapter introduces QDAC-based TPM architecture for low-power, low-noise and wideband frequency modulation. The specifications of the 10 GHz chirp synthesizer which is part of a 60 GHz FMCW radar system are derived. The proposed QDAC-based frequency modulator architecture is described, and its advantages over the conventional VDAC-based and switched-capacitor Digital-to-Analog Converter (DAC)-based architectures are discussed. An insight into the proposed nonlinearity calibration is illustrated, followed by its detailed mixed-signal implementation is elaborated. The design choices of each PLL building blocks are evaluated and key building blocks design are described. Implemented in a 28 nm Complementary Metal-Oxide Semiconductor (CMOS) process, the prototype consumes 11.7 mW to generate a 23.6 MHz/ \(\upmu \) s sawtooth chirp-slope with 28 kHz rms-frequency-error for 1.21 GHz chirp-bandwidth.