Q-CODA: Co-designing Quantum Codes and Architectures for Hardware-Aware Quantum Error Correction

Quantum computers promise profound scientific advances, but their practical realization is impeded by ubiquitous errors. Quantum error correction (QEC) provides techniques to detect and correct errors, enabling reliable quantum computation. However, conventional QEC codes require prohibitive physical qubit overheads. This work introduces customized protocols to reduce QEC resource costs tailored for near-term superconducting hardware. We propose code constructions including optimized surface code geometries and concatenated inner code layers to improve qubit efficiency. A comprehensive noise modeling methodology is outlined to capture complex multi-qubit error processes using Lindblad master equation simulations of device Hamiltonians. The realistic device noise model is essential for evaluating tailored QEC protocols. Hardware-aware decoding algorithms based on recurrent neural networks can potentially further suppress logical faults by avoiding oversimplified assumptions. We introduce a modeling framework to quantify overhead reductions from our coordinated techniques. While considerable research remains to realize practical solutions, this work delineates promising directions by bridging hardware, software, and theory via code co-design, accurate noise models, and quantified gains. The tailored techniques offer the potential to progress toward viable fault tolerance in noisy intermediate-scale quantum devices.