Secure Physical Design

An integrated circuit is subject to a number of attacks including information leakage, side-channel attacks, fault injection, malicious change, reverse engineering, and piracy. The majority of these attacks take advantage of the physical placement and routing of cells and interconnects. Several measures have already been proposed to deal with security issues of the high-level functional design and logic synthesis. However, to ensure end-to-end trustworthy IC design flow, it is necessary to have security sign-off during physical design flow. This chapter presents a secure physical design roadmap to enable end-to-end trustworthy IC design flow. The chapter also discusses the utilization of AI/ML to establish security at the layout level. Major research challenges in obtaining a secure physical design are also discussed.