On-Chip Evaluation of Voltage Drops and Fault Occurrence Induced by Si Backside EM Injection

Cryptographic modules are vulnerable to fault injection. Electromagnetic fault injection (EMFI) uses electromagnetic (EM) waves as a means of introducing faults into target circuits. These days, EMFI draws attention as a real threat to cryptographic circuits because of its inherent advantages. Although EMFI has become popular, there are only a few works on EMFI at the lowest physical level. In this paper, we experimentally show that EMFI induces negative voltage drops with outstandingly large negative amplitude and with layout-dependent localization on power delivery network (PDN) inside the chip. The drops are very much relevant to failures that occur in digital circuits. A test chip in a 180 nm CMOS technology embeds six crypto cores of 128 bits AES and on-chip voltage waveform monitor. The chip is assembled in flipped-chip packaging and attempted by EMFI from its Si substrate backside. EMFI uses an antenna coil with the diameter of 1 mm, scans and contacts it over the backside chip surface within the area of 3 mm × 4 mm. With our detailed, chip-level and multi-physics exploration of EMFI delivered in this paper, we find the need of more in-depth understandings on EMFI mechanisms from physics viewpoints, toward the design of EMFI resiliency among crypto cores backed with accurate and efficient coupling models from PDN to transistor-level digital circuits.