Synthesis of Fault-Tolerant QCA Logic Circuit Using Cellular Automata

The CMOS technology faces significant obstacles in digital logic design because of its reduced device density and increased power consumption. Quantum-dot-cellular automata (QCA) has arisen as a promising alternative to address these limitations. The basic unit for constructing logic circuits in QCA is the QCA cell, comprising four quantum dots with two electrons. In QCA, the fundamental building blocks are the majority gate and inverters. Clocking has a significant contribution in guaranteeing proper synchronization and data propagation within a circuit. Additionally, regular clocking addresses manufacturing challenges in the nanoscale domain and promotes scalability. Nonetheless, defects continue to be a worrisome issue in the realization of nanoscale circuits. In this regard, this work demonstrates the synthesis of fault-tolerant QCA circuits utilizing Cellular Automata (CA) rules. The Hardware Description Language (HDLQ) and QCADesigner simulators serve this particular function.