Analysis of Clock Tree Buffer Degradation Caused by Radiation

Current commercial field programmable gate arrays (FPGAs) take serial configuration architecture to realize their programmability. However, the serial configuration circuit is very weak for radiation in terms of both total-ionizing-dose and soft-error tolerances. If radiation permanently breaks even only a few transistors inside an FPGA, the serial configuration circuit is easily down at an extremely high probability. Always, the total-ionizing-dose tolerance of radiation-hardened FPGAs is limited to up to 2 Mrad. In order to increase the total-ionizing-dose, a radiation-hardened FPGA with a triple-modular-redundant configuration circuit that can achieve 730 Mrad total-ionizing-dose tolerance has been developed. The radiation-hardened FPGA can allow a number of transistors to be broken by radiation and can have a large clock skew margin. This paper presents the analysis result of the clock tree buffer degradation caused by radiation based on the experimental result of the degradation of look-up tables and clarify the suitable clock skew margin of the radiation-hardened FPGA.