A Flexible Mixed-Mesh FPGA Cluster Architecture for High Speed Computing

This paper focuses on integrating multiple FPGAs for High-Performance Computing (HPC) applications with a priority on computational capability and reliability. It introduces a reliable inter-FPGA cluster architecture, detailing experimental results of FPGA communication layer performance and hardware management using FreeRTOS on a TMR Microblaze processor. The communication layer features a hardware core for inter-FPGA communication performance, evaluated on a multi-FPGA cluster testbed. Results demonstrate high-speed data transfer and fault tolerance. The hardware manager enhances system flexibility, enabling dynamic task scheduling for hardware accelerators. The paper’s benchmark application is an image-processing pipeline, showing practical applicability with data throughput exceeding 67.4 Gb/s and low latency of 288 ns.