Secure eFPGA Configuration: A System-Level Approach

Field Programmable Gate Arrays (FPGAs) have repeatedly proven their importance in modern computing, delivering high flexibility while minimizing performance trade-offs and engineering costs compared to Application-Specific Integrated Circuits (ASICs). However, to achieve this level of flexibility, FPGAs require configuration, presenting a non-trivial initialization procedure accompanied by the inherent hardware security challenge focused on protecting the confidentiality of the user’s sensitive configuration data. This paper presents the Programming Management Unit (PMU) as an open-source core to address embedded FPGA (eFPGA) configuration and bitstream protection with a co-design implementation approach. The PMU hardware is meant to be adaptable for easy integration into open-source projects, providing a nexus for standardized communication protocols, cryptographic cores, and eFPGA configuration memory architectures. Moreover, this project aims to support the entire end-to-end configuration procedure, spanning from bitstream generation to eFPGA configuration memory, necessitating a software-based frond-end for encipherment, encoding, and delivery to PMU hardware. Showcasing the PMU within a practical context, this paper details an application where the PMU interfaces with JTAG, AES, SHA, and OpenFPGA eFPGA fabric carried out in the Skywater130 technology node. This demonstration highlights the PMU’s efficiency by illustrating the system-level trade-offs between area, power consumption, configuration time, and security protocols.