Compact Modelling of Wafer Level Chip-Scale Package via Parametric Model Order Reduction

The interconnect reliability of a packaged chip on the printed circuit board is a major requirement that should be met for assembling microelectronics. The solder connection fatigue is one of the main failure modes. It is caused by the mechanical stress due to thermal expansion. In this work, the finite element model of a package on the printed circuit board is built and the solder joint analysis is performed within a thermo-mechanical simulation. For efficient studies of the temperature impact on the solder joints, we present a successful application of parametric model order reduction for constructing a compact model starting from the full order finite element model. Temperature dependent Young’s modulus, a parameter, which appears on both the left-hand and the right-hand side of the spatially discretized model, is preserved in the symbolic form within this compact model.