Design of Low Power and Energy Efficient Write Driver with Bitline Leakage Compensation for SRAM

High performance applications demand faster SRAM with low power and energy consumption, wherein the write driver is a critical component governing its write performance. The existing write drivers fail to optimize all the parameters simultaneously due to bitline leakage-discharge current trade-off. In this paper, a novel write driver is presented, which uses a unique leakage-compensation mechanism to overcome this trade-off. The designs are implemented at 32 nm and are compared under PVT-variations with 3σ global process and frequency variations. The results show that the proposed design outdo all the existing designs, providing up to a 9.9% improvement in write delay, with a 26.75%, 26.03% and 29.13% reduction in write power, energy per switching activity, and differential bitline voltage, respectively, at 1.1 V, 27 ℃ and TT corner. Thus, the design is suitable for a multitude of applications due to its low write delay, reduced power consumption and increased energy efficiency.