DSP Runtime Emulator on FPGA: Implementation of FIR Filter Using Neural Networks

Digital Signal Processors (DSPs) are processors designed and optimized to perform operations on signals. Although DSPs continue to be used for signal processing, more flexibility is required in modern systems, including digital signal processing. Field-Programmable Gate Arrays (FPGAs) offer this flexibility and control over the hardware design process while providing the necessary DSP operations. Moreover, digital filtering is one of the widely used operations in digital signal processing, especially the Finite Impulse Response (FIR) filter for its stability. However, the FIR filter requires more taps to perform filtering accurately which results in a slower execution time, and more memory requirements. In this paper, a real-time emulator for a lowpass FIR filter design is implemented by designing a neural network to predict the filter operation on the FPGA-based Nios II soft-core processor on the DE2-115 and the DE10-Lite boards. The performance of the neural network for a 15-tap lowpass FIR filter is evaluated and benchmarked against a software implementation of the FIR filter operation.