SRISC: Open Source Soft Processor Side Channel Analysis Attack Framework Using RISC-V

Side channel analysis (SCA) attacks on soft processor systems (such as RISC-V and LEON3) are typically performed on FPGA prototyping boards. For the first time, this paper presents a RISC-V-based soft processor SCA framework (referred to as SRISC) to perform power-based, electromagnetic radiation-based and execution time-based SCA attacks against cryptographic algorithms and to test countermeasures on soft processor systems. The proposed SRISC framework is demonstrated on a commercial side-channel analysis attack board, SASEBO-GIII (referred to as SRISC-SASEBO). SRISC consists of hardware modules to calculate cryptographic operations using hardware circuits. As a case study to test the implementation of a countermeasure, a balanced AES countermeasure is discussed to show the effectiveness of building hybrid countermeasures (which use both hardware and software components–hardware/software co-design) to reduce the information leakage to mitigate power analysis attacks. The software implementation of the balanced AES countermeasure revealed 14 bytes (of 16 bytes) of the secret key in 18,000 encryptions. The balanced hybrid AES countermeasure revealed only eight bytes (of 16 bytes) of the secret key for the same number of encryptions making software-hardware co-design countermeasures more promising to mitigate power analysis attack vulnerabilities.