A Dual-BRAM Solution for BTSx Instructions on FPGA Processors

Processing time is very important in biomedical equipment and affects decision taking, result interpretation or calculus for a variety of targeted applications: ECG, PPG or SpO2. To answer the need for rapid medical application prototyping, we present a solution to optimize instruction execution on FPGA processors. The targeted applications account for multiple input signal acquisition in a scenario of body worn sensors. This work addresses the implementation of bit/byte-oriented register operations, reducing the operating time of the processor by simultaneously reading and writing from/in the memory block. During customary execution, bit/byte test skip instructions introduce a one clock-cycle delay. This paper proposes a dual-instruction memory solution, implemented using block RAM modules, to eliminate the respective execution delay. The proposed solution enables the simultaneous retrieval of two instructions which would follow the execution path, regardless whether the skip decision has been taken or not. The VHDL implementation of the proposed solution was simulated in Vivado and was validated on an Artix7 35T and a Kintex Ultrascale+ FPGA respectively.