Designing a Graphics Accelerator with Heterogeneous Architecture

The article discusses the architecture of a graphics accelerator, based on a combination of general-purpose processor cores and pipeline accelerators for performing operations with matrices and transcendental operations. The article proposes a general architecture for GPUs of this type and suggests the main options for computing nodes designed to implement target group algorithms. In order to reduce technical and organizational risks, it is planned to simplify the hardware component of Very Large Scale Integrated Circuits (VLSI) and transfer the functions of managing calculations to embedded software, for which control processor cores have been introduced into VLSI. The VLSI project involves the development of a GPGPU-class computing accelerator, in which the ability to work with three-dimensional graphics is an additional feature. This allows you to take advantage of an architecture based on a large number of simple computational cores, using such VLSI in conjunction with a general-purpose processor.