Design of a Pipeline Computing Module as Part of a Specialized VLSI

The article discusses the process of designing a computing node based on a synchronous pipelined architecture for operation as part of a specialized VLSI. During the design process, individual pipeline levels generate conflicting requirements for the implementation of individual nodes and the pipeline as a whole. This requires resolution in the form of finding suboptimal pipeline tuning options. The approach discussed in the article involves the use of a high-level synthesizer to distribute calculations between individual stages of the pipeline, which allows to reduce the signal delay at the expense of increased pipeline latency Analyzing the interaction of the pipelined calculator with other components of the computing system makes it possible to include in the model of estimated characteristics the cost of waiting for the result. This method, as the simulation results have shown, significantly corrects the approaches to finding the optimal solution, which also includes the costs of the system resources as a whole. Preliminary estimates have received qualitative confirmation when synthesizing modifications of the test pipeline in CAD FPGA.