Hardware Implementation of MRO-ELM for Online Sequential Learning on FPGA

This paper presents a parallel hardware accelerator for an online variant of the extreme learning machine (ELM) algorithm, called mixed-norm regularized online ELM (MRO-ELM). ELM is a training algorithm for feedforward neural networks that has been widely adopted in the literature. The proposed parallel architecture is implemented on a field-programmable gate array (FPGA) and designed for classification tasks. It is designed to be scalable and reconfigurable for different problem sizes, and can be used for various numbers of hidden neurons. Among the existing studies, the proposed architecture is the first hardware implementation that has norm regularization with parallel processing capability. The implementation results for the proposed hardware accelerator are reported in terms of hardware efficiency and they show that the proposed design has lower resource utilization than existing parallel implementations.