A Low Noise 10-Bit 59.41dB SNR SAR ADC Using Chopper Comparator for Biomedical Applications

This paper presents a low noise 10-bit 59.51 dB SNR successive-approximation-register (SAR) analog-digital-inverter (ADC) using the chopper comparator for biomedical applications. The proposed SAR ADC uses a low-power two-stage chopper amplifier (TSCA) to achieve low noise and low power consumption. However, the TSCA is attached to an unlikely offset caused by the process variation, which leads to ripple appearing at the output. Therefore, the proposed chopper comparator uses an offset cancelation loop to mitigate the output ripple. In addition, the TSCA with a self-calibrating input stage is used in the proposed comparator to achieve the lowest delay slope and susceptibility to supply the circuit and have common mode fluctuations compared to prior works. The proposed SAR ADC, which was simulated in a 180 nm CMOS technology, occupies only 0.457 mm2 active area. According to simulation results, the prototype SAR ADC achieves a signal-noise ratio (SNR) of 59.41 dB, a signal-to-noise and distortion ratio (SINAD) of 59.06 dB, and an effective number of bit (ENoB) of 9.52 bit while draws a power of 97 µW leading to the Figure-of-merit (FoM) of 24.1 dB is achieved. Therefore, the proposed SAR ADC is an effective approach for biomedical applications.