Design of Digital Integrated Circuits by Improving the Characteristics of Digital Cells

This chapter is devoted to the development of methods and principles for improving the main characteristics of digital standard cell (SC), which will allow to significantly increase the efficiency of the design process and improve the main characteristics and parameters of ICs, which are based on them. Principles for the development of effective IC design tools by improving the characteristics of SCs are proposed, which, at the expense of machine time, ICs’ timing parameters, and insignificant deterioration of area, allow to significantly improve SC-based IC main parameters: power consumption, supply rails’ voltage drop, routability, etc. SC input/output (I/O) pin accessibly optimization method is developed, in which, due to special logic synthesis, placement, and routing of all SCs in the library, about 9.4 times of reduction in testing time has been achieved at the expense of a decrease of approximately 11.2% in the number of cell abutments. Method for pin accessibility prediction and optimization is proposed, in which, due to inter-cell spacing rule generation, design rules’ violation count has been decreased by 47%, in the case of only a 23% increase of the total tool runtime. Method for SC optimization for design with different height cell mixed usage is proposed, in which, due to multiple height cells integration into one design, about 14.3% of timing parameters’ optimization is achieved, in the case of only 12.8% increase of circuit’s power consumption. A neural network-based “sleep mode” control method is proposed for the use of a low-power consumption-oriented circuit design, in which, due to the introduction of the controlled-power supply cells, an average reduction of approximately 12% in power consumption has been achieved, by only increasing the circuit area by approximately 5–28%. A method of metal dummy fill is proposed, in which, due to the connection of special filling layers to the power supply rails, an average voltage drop of approximately 11.9% was obtained, with an increase of approximately 4.4% in the total parasitic capacity of the circuit.