Design Methods of Integrated Circuits, Working Under Non-standard Operating Conditions

This chapter is devoted to the solution of current issues in IC design, operating in non-standard conditions, and the development of new methods. Methods for designing ICs that work in non-standard operating conditions are proposed, which, meeting modern requirements, will significantly reduce changes of external conditions and deviations caused by aging effects by increasing the occupied area on the die and power consumption within acceptable limits. A method has been developed to reduce the offset in comparators caused by aging effects, in which the operating conditions of transistors during power down state of the circuit have been improved due to addition of transition gates; the offset has been decreased about ten times by 4.81% maximum increase of the area. A technique is proposed to minimize the offset caused by temperature changes in the receiver of ICs, in which, due to the usage of current DAC, it was possible to reduce offset by a maximum of 19 times by 43.2% decrease of the area on the die and 7.2% increase of power consumption. A method is proposed to reduce the deviations caused by voltage and temperature changes in DDLs, in which by adding negative feedback, it was possible to reduce the delay range of DDL by 56.04% caused by external condition changes by 23.1% area increase.