Means to Accelerate Transfer of Information Between Integrated Circuits

This chapter is devoted to the development of means in I/O blocks that will allow to increase the frequency of the transmitted signal and to level the distorted signal. Effective approaches in terms of time constraints for developing means of increasing the speed of sequential information acquisition in integrated circuits have been proposed. The embedded nodes and the structure of the architecture make it possible to significantly increase the data transfer and processing frequencies if the area occupied on the die is within the allowable limits. An asynchronous linear equalizer is proposed: an embedded binary code negative control system that, with positive feedback and linearity calibration, provides almost twice as fast signal equalization by only 11% increase in the area occupied on the die. A method of increasing the speed of the decision feedback equalizer has been proposed, which, due to the introduction of low-input high-speed comparators, doubles the frequency of data processing by only 16% increase in power consumption. A method for constructing a signal processing system transmitted by Pulse Amplitude Modulation (PAM4) is proposed, which, due to data storage and parallel tap processing, increases the data transfer rate by about 50% with an increase of about 12.2% in the receiver area on the die.