Scalable and Efficient Architecture for Random Forest on FPGA-Based Edge Computing

This paper proposes a scalable and efficient architecture to accelerate random forest computation on FPGA devices targeting edge computing platforms. The proposed architecture with efficient decision tree units (DTUs) executes samples in a pipeline model for improving performance. Moreover, a size-effective memory organization is also introduced with the architecture to save the on-chip block ram used for reducing the latency and improving working frequency of the implementation system on FPGA devices. We target edge computing platforms that suffer from the limitations of resources and power consumption. Therefore, the proposed architecture can reconfigure the number of DTUs according to the target platform’s available resources. We build a system with a PYNQ Z2 FPGA board for testing, validating, and estimating the proposed architecture. In this system, we exploit different numbers of DTUs, from 1 to 15, to test our scalability. Experimental results with certified datasets show that we achieve speed-ups by up to 170.39 \(\times \) and 90.27 \(\times \) compared to Intel core i7 desktop version and core i9 high-performance computing version processors, respectively.