Generalized Fractional-Order Complex Logistic Map and Fractals on FPGA

This paper introduces a generalized fractional-order complex logistic map and the FPGA realization of a corresponding fractal generation application. The chaotic properties of the proposed map are studied through the bifurcation behavior and maximum Lyapunov exponent (MLE). A concise fractal generation process is presented, which results in designing and implementing an optimized hardware architecture. An efficient FPGA implementation of the fractal behavior is validated experimentally on Artix-7 FPGA board. An example of fractal implementation is verified, yielding a frequency of 24.34 MHz and a throughput of 0.292 Gbit/s. Compared to recent related works, the proposed implementation demonstrates its efficient hardware utilization and suitability for potential applications.