Void Nucleation in a Through Silicon Via (TSV): Unraveling the Role of Tilt Grain Boundaries Through Atomistic Investigation

Through Silicon Via (TSVThrough silicon via (TSV)) is a technique used in three-dimensionalThree-dimensional (3D) integrated circuit (IC) packaging to vertically stack layers for the purpose of establishing electrical and mechanical connections. Nevertheless, TSVThrough silicon via (TSV) faces certain challengesChallenges that pose risks to its reliabilityReliability, many of them originated from void formation. Despite its importance, considering the challengesChallenges for experimental analysis of the phenomenon, there are a lot of uncertainties about the mechanism of void nucleationVoid nucleation. An important parameter affecting void nucleationVoid nucleation under stress is the grain type and orientation. This study aims to understand this effect through a systematical analysis, using molecular dynamics simulationsMolecular dynamics simulation. Void formation during tension in the tilt grain boundaryTilt grain boundary and within the grain of a face-centered cubic (FCC) Cu bicrystal is examined. Three misorientation axes— < 100> , < 110> , and  < 111 >—with various tilt angles are explored. This study suggests that the level of strain that leadsLead to void nucleationVoid nucleation depends on the dislocation network that exists at the grain boundaryGrain boundaries. Dislocation evolutions throughout loading are examined to define the mechanism of void formation.