Study of Equivalence in Systems Engineering Within the Frame of Verification

In the discipline and practice of Systems Engineering, we typically derive verification models based on implicit, heuristic assumptions rather than science-based approach. For example, when we define verification requirements, we may optionally define a desired fidelity of a verification model as to its representativeness to a final product in the qualitative terms of high, medium, or low fidelity. Is this fidelity ever confirmed? Or is the fidelity simply assumed? Given that the intent of verification is to infer adherence of a system design to its corresponding system requirements; if the fidelity is assumed, then there exists an uncharacterized challenge to verification. Furthermore, in the pursuit of theoretical foundations of Systems Engineering, the derivation of verification models is an unexplored research territory. This chapter summarizes the findings from a research dissertation on the study of equivalence in Systems Engineering within the frame of verification. The dissertation leveraged systems theory principles to explore the relationships necessary and sufficient to define verification models based on framing between the verification artifacts: system requirements, system design, verification requirements, and verification models.