Area Efficient and Ultra Low Power Full Adder Design Based on GDI Technique for Computing Systems

The relevance of ultra-low-voltage (ULV) operation for attaining minimal energy usage has increased recently. The fundamental building element of computational arithmetic in many computer and signal/image processing applications is the full adder. An innovative 1-bit hybrid adder circuit that uses both multi-threshold voltage (MVT) transistor logic and GDI (gate-diffusion input) logic is disclosed. The suggested motivation of the Multi Threshold Voltage-gate-diffusion input hybrid adder design is to furnish low energy efficient utilization with a small footprint. Standard 45 nano-meter CMOS process technology is used to simulate the suggested hybrid architecture with a ULV of 0.2 V. The suggested design made considerable improvements in contrast to the previous published designs, yielding >57% and 92% reductions Using only 14 transistors in the Energy and Delay Product respectively, according to the post-layout simulation findings. The suggested design technique produces full functionality, which shows resistance against the processes of global, local variations. The suggested design offers >57% energy efficient compared to the current efforts, according to energy measures that are adjusted for 32 and 22 nm technologies.