Full Swing Logic Based Full Adder for Low Power Applications

During the design of Application-Specific Integrated Circuits, a whole adder logic circuit plays a significant role. The full adder is a fundamental part of the majority of VLSI and DSP applications. Power consumption in full adders is one of the key factors; hence it is necessary to build full adders with low power consumption. Full adders are developed in this work employing full swing AND, OR, and XOR gates and compared with pass transistor logic (PTL) based AND, OR, and XOR gates, and complementary metal oxide semiconductor logic (CMOS) based AND gate, OR gate, and XOR gate. The Mentor Graphics Tool is used to construct and simulate every planned circuit. After receiving simulation data, we compared the power consumption, delay and PDP of several complete adder-based logic designs. In the proposed full swing XOR, the power dissipation and delay is decreased by 10.5% and 9.8% respectively and hence the full swing full adder PDP is decreased by 0.6%. As compared to alternative full adder designs based on logic, full swing by using gates like AND gate, by using the OR gate, and with the help XOR gate, full adder design consumes less power and hence suitable for low power applications.