Design and Analysis of a Voltage Schmitt Trigger in 4H-SiC CMOS Technology

A CMOS Schmitt trigger based on 4H-SiC CMOS 2 \(\mu m\) technology is presented. A standard topology of the trigger is used, but the classical design equations are inapplicable due to the different 4H-SiC MOSFETs electrical behaviours compared to silicon ones, like high traps density at oxide/semiconductor interface. Numerical simulations at various temperatures between 298K and 573K have been performed, showing a variation of the Schmitt trigger hysteresis window even to \(7.07\%\) . To asses process variability effects, Monte Carlo analysis has been performed at 298K showing a trigger high, \(V_H\) , and low, \(V_L\) , threshold voltages deviations, respectively, of \(7.15\%\) and \(9.97\%\) from their nominal value. Finally, MOSFETs threshold voltage has been identified as the process parameter that mostly affect circuit operation.