A Binary Pattern Matching Task Performed in an ePCM-Based Analog In-Memory Computing Unit

This paper shows the results related to a Binary Pattern Matching (BPM) task executed on an Analog In-memory Computing (AIMC) unit based on an embedded Phase-Change Memory (ePCM), both designed in a 90-nm CMOS STMicroelectronics technology. The Hit Rate in pattern recognition is characterized and modeled in different scenarios, in order to evaluate the influence of cells Conductance Time Drift (CTD) in a real application. In particular, two PCM multilevel programming algorithms and different cells conductances are considered, and their effects on CTD are experimentally observed. Results suggest that the adoption of a SET staircase (SSC) sequence implies a lower CTD on PCM cells with respect to a RESET Staircase (RSC) sequence, as well as an increased Hit Rate, even with lower levels of employed conductance.