Benchmark Circuits for Single Flux Quantum Integrated Systems

Superconductive single flux quantum (SFQ) technology is one of the most promising beyond CMOS technologies for large-scale, high-performance computing systems. The operating frequency of SFQ circuits may exceed hundreds of gigahertz while dissipating several orders of magnitude lower power, including the refrigeration. Recent advances in SFQ manufacturing technology have enabled significantly higher levels of integration and system complexity. Further advancements in SFQ systems integration require improved design methodologies and flows. The lack of SFQ specific benchmark systems complicates the development and evaluation of these SFQ design flows. This limitation is particularly relevant to the development of physical design tools since existing CMOS benchmark systems are not easily adapted to support SFQ technology. In this chapter, a suite of SFQ specific interconnect routing benchmark systems is presented. The benchmark circuits support the evaluation of data signal, clock signal, and bias current routing algorithms. Due to the gate-level pipelining inherent to SFQ logic, path balancing using D flip flops is required to ensure consistent logic depth and correct operation. Popular CMOS benchmark circuits are converted into SFQ technology, producing SFQ circuits with over 100,000 logic gates. Based on Synopsys EDA tools, the layout of these systems is generated for the MIT LL SFQ5ee technology. Rows of logic cells and passive transmission lines are also included within the layout to manage the interconnect length and delay. The benchmark circuits are openly available to evaluate and enhance state-of-the-art and next-generation physical design of VLSI complexity SFQ systems.