Wave Pipelining in DSFQ Circuits

Dynamic SFQ (DSFQ) circuits are a promising circuit topology for asynchronous SFQ logic. The operation of DSFQ circuits, however, significantly differs from both CMOS logic and conventional synchronous RSFQ logic. Novel design methodologies are necessary to synthesize DSFQ circuits while increasing performance and decreasing area. The path balancing process, essential for RSFQ circuits, is less important for DSFQ. Path delay balancing, however, can increase the performance of DSFQ circuits by enabling wave pipelining. In this chapter, different path balancing approaches for DSFQ circuits are evaluated and compared to equivalent RSFQ circuits. A partial path balancing methodology is described and characterized, where path balancing is first applied to the critical paths. This methodology enables wave pipelining in DSFQ circuits and reduces the period between data waves.