Design Guidelines for ERSFQ Bias Networks

ERSFQ is an energy-efficient, inductive bias scheme for RSFQ circuits, where the power dissipation is drastically lowered by eliminating the bias resistors while the cell library remains unchanged. The ERSFQ bias scheme requires multiple circuit elements—current limiting Josephson junctions, bias inductors, and feeding Josephson transmission lines (FJTL). In this chapter, parameter guidelines and design techniques for ERSFQ circuits are presented. These guidelines enable more robust circuits resistant to severe variations in the supplied bias current. Trends are considered, and advantageous tradeoffs are discussed for the different components within a bias network. The guidelines provide a means to decrease the size of a FJTL and thereby reduce the physical area, power dissipation, and overall bias current, supporting further increases in circuit complexity. A distributed approach to an ERSFQ FJTL is also presented to simplify the placement process and minimize the effects of the parasitic inductance of the bias lines. This methodology and related circuit techniques are applicable to automating the synthesis of bias networks to enable large-scale ERSFQ circuits.