Synchronization

The speed of operation in a synchronous circuit is controlled by the clock distribution network. Most RSFQ circuits require a large multi-gigahertz clock network, as unlike CMOS, most logic gates are clocked. AQFP circuits however utilize a multiphase AC power network for synchronization. In a self-timed asynchronous circuit, where a global clock network is absent, handshaking gates and protocols are necessary. Timing tolerances in all of these systems are extremely narrow, and an effective clock network is required for robust high-performance operation. The optimal design of the clock distribution network, providing robustness against timing variations, and proper organization of the handshaking circuits are crucial to maintain correct operation of multi-gigahertz systems. Techniques providing solutions to these issues in superconductive circuits are also described in this chapter. Existing pulse-based clock distribution topologies are introduced and related tradeoffs are described. Asynchronous techniques which do not require a global clock are discussed. Synchronization in AC-biased circuits, utilizing a different clocking mechanism, is also described.