HLDD-Based Test Generation for RISC Processors

In this chapter, we develop a novel approach to automated Software-Based Self-Test (SBST) generation for the RISC processor cores using HLDDs derived from the instruction set and the architecture description of the processor under test. To overcome the fact that processors’ implementation details are often unavailable, we developed a novel implementation-independent test generation method. To cope with the complexity of the problem, we divide the processor into modules, each module formally into control and data parts, and generate tests for them separately. For the data parts, we apply a pseudo-exhaustive test, whereas, for the control parts, we have developed a novel generic HLDD-based implementation-independent control fault model that covers a very large class of structural and functional faults without explicitly listing them.