High-Level Decision Diagrams

In this chapter, we generalize the decision-based concept of logic-level SSBDDs to apply it for modelling digital systems at higher abstraction levels with High-Level Decision Diagrams (HLDDs). The chapter presents the theoretical basics of HLDDs, shows the topological similarity of low- and high-level decision diagrams, and describes several methods of synthesis of HLDDs. This includes synthesis methods from different description models of digital systems at higher levels, such as RT-level, functional or behaviour levels, and the level of Instruction Set Architectures (ISA) for microprocessors. Several applications of HLDDs in the test field are discussed, such as code coverage measurement, hierarchical fault simulation by combining SSBDDs and HLDDs, and hierarchical test generation for sequential circuits. We also present the HLDD-based automated test pattern generator DECIDER developed by the authors.