Logic-Level Fault Simulation

In this chapter, we present different applications of SSBDDs and S3BDDs in the field of simulation of digital circuits. We have developed algorithms for parallel pattern simulation by tracing the paths in the BDDs in parallel for all bits of the data words. For timing analysis and detection of hazards in the circuit, we present a method of multi-valued simulation with SSBDDs, based on the 3- and 5-valued algebras. A novel idea of parallel pattern back-tracing of critical paths was implemented using S3BDDs for detecting all detectable faults in a combinational circuit by a given set of patterns using a single simulation run. Novel simulation-based methods are proposed for the identification of critical paths in digital circuits.