Design Strategies for Very-Low-Voltage Dickson CPS

This chapter is focused on the design strategies for very-low-voltage Dickson CP implementations that are particularly suited for the energy harvesting applications. Three innovative solutions are discussed. A first topology exploits for the CTS the combination of NMOS and PMOS transistors with gates connected to internal nodes of the CP, thus enhancing the overdrive voltage of the switches. A second CP topology, named Hybrid Latched CP, is shown as suited for subthreshold regime. The topology is useful to realize PMU used to boost and efficiently adapt the output voltage of a thermoelectric generator (TEG) whose output is as low as tens of milli-volts. And, a recent solution based on current-mode body biasing (CMBB) technique is discussed. This solution requires a simple control circuit (current starver) and allows to easily and safely control the bulk to drain/source (S/D) junctions.