Design Strategies for Low-Power Dickson CP Applications

This chapter gathers two different solutions aimed to the reduction of the energy consumed by the converter during the wake-up phase. In particular, in the first section, a solution based on the reduction of the voltage amplitude of the clock signal is presented. It represents a simple but very effective design strategy to increase power conversion efficiency. In the second section, it is shown that with node pre-charging, simply implemented by means of few auxiliary diodes and parasitic junctions, the CP retains the charges in the pumping capacitors when the harvesting power source is not able to feed the system, thereby reducing the input energy, and the rise time too, during the start-up phase.